1. Field of the Invention
The invention generally relates to high-density non-volatile memory circuits, and more particularly to memory devices based on phase-change materials.
2. Description of the Related Art
Memory devices based on phase change materials (PCM) are generally non-volatile, are capable of high read and write speeds, and are compatible with a relatively simple cell design. The phase change memory element is typically switched between a largely amorphous (high resistance) state and a largely crystalline (low resistance) state. Typical materials suitable for such electrically switchable phase-change memory elements are based on chalcogenides. These materials are typically switched by the application of heat generated by the passage of electrical current through the material. The cell state is determined by measurement of the cell resistance.
More specifically, heating the high resistance (amorphous) material to a set temperature, Tc, changes the phase of the low resistance (crystalline) state. As taught by U.S. Pat. Nos. 5,825,046 and 6,087,674, the complete disclosures of which are herein incorporated by reference, switching is accomplished by direct heating. Heating to a higher temperature, Tm, and quenching resets the PCM to its original phase. Thus, the set temperature, Tc, is associated with the change in phase from an amorphous state to a crystalline state. Heating to the reset temperature and quenching resets the chalcogenide to its amorphous phase.
Such phase-change memory is compatible with a crosspoint architecture, as is taught in U.S. Pat. No. 6,579,760, the complete disclosure of which is herein incorporated by reference, where the cell size can approach the minimum cell size of approximately 4F2 (where “F” stands for “feature” as in minimum resolved feature), which is effectively the minimum cell size that can be uniquely and instantaneously addressed by electrical interconnects, for a two interconnect level design. In the context of a device size, 4F2 means that the area of the device is 4 times the minimum resolvable feature size squared. A lithography with a resolution of 100 nm could be used to create devices with an area of 4×(10−7)2=4×10−14 cm2. Combined with the demonstrated high-speed performance and its intrinsic non-volatile nature, phase change memories have the potential to compete with all existing memory devices.
In the U.S. Pat. No. 6,579,760 patent, a multilayer stack is first deposited containing a conduction layer for the lines of the first direction as well as the phase-change material and diode and heater layers. The whole stack is then patterned into lines. Then, oxide material is coated onto the lines and the structure is planarized. As these memory devices are pushed to higher densities, this planarization will become difficult and will require an unprecedented level of control. Indeed, the level of control required may not be achievable.
Accordingly, it is desirable to eliminate the planarization requirement. It is also desirable to minimize the number of processing steps, thereby increasing yield and reducing manufacturing costs.